FIG. 1 illustrates a related art switchable capacitive element 10 connected to a radio frequency (RF) line 12. The switchable capacitive element 10 has a field effect transistor (FET) device stack 14 and a capacitor CRLW. The FET device stack 14 has a plurality of FET devices 16 coupled in series. Each of the plurality of FET devices 16 includes a drain contact D, a source contact S, a gate contact G, and a body contact B. The capacitor CRLW has a capacitance and is also coupled in series with the FET device stack 14. When the FET device stack 14 operates in a closed state, the switchable capacitive element 10 presents the capacitance of the capacitor CRLW to the RF line 12. With regard to an RF signal 18 propagating on the RF line 12, the switchable capacitive element 10 provides a shunt path for the RF signal 18 to ground.
However, when the FET device stack 14 operates in the open state, the switchable capacitive element 10 does not present the capacitance of the capacitor CRLW to the RF line 12. Instead, the switchable capacitive element 10 presents a minimum capacitance, which ideally is at zero but in practice may be the result of parasitic capacitances within the switchable capacitive element 10. The FET device stack 14 ideally operates as an open circuit and thus, theoretically, the FET device stack 14 does not conduct any of the RF signal 18. Of course, in practice, the FET device stack 14 may not operate precisely as an open circuit, but rather may simply present a very high impedance. Accordingly, some leakage currents are conducted through the FET device stack 14 during the open state, but these are generally low enough to be considered negligible. By stacking the plurality of FET devices 16, a voltage of the RF signal 18 can be distributed across the plurality of FET devices 16 when the FET device stack 14 is in the open state. This allows the FET device stack 14 to handle higher voltage RF signals 18.
Next, to provide the appropriate biasing voltages for operating the FET device stack 14, the switchable capacitive element 10 includes a related art control circuit 20 having a DC voltage source 22, a negative voltage source 24, a plurality of switches 26A, 26B, 26C, 26D, and 26E (referred to collectively as switches 26), and a bias control device 28 that controls the switches 26. The bias control device 28 controls the plurality of switches 26 to bias a gate voltage at the gate contacts G and a body voltage at the body contacts B in accordance with Table I below.
TABLE ISwitch StateGate VoltageBody VoltageOpen State−Vbias−VbiasTransition State 1Ground−VbiasTransition State 2GroundGroundClosed State+VbiasGround
Each of the drain contacts D and the source contacts S of the plurality of FET devices 16 is biased at ground, or possibly at a different reference voltage, during both the open state and the closed state. The voltage at the drain contacts D and the source contacts S does not change with respect to the reference voltage (i.e., in this example, ground). However, by biasing the gate contacts G at the voltage −Vbias, the channels of the FET devices 16 are pinched off and a buffer voltage is provided that ensures that the RF signal 18 does not turn on the plurality of FET devices 16 during the open state. To prevent reverse bias diodes from being formed between the body of each of the plurality of FET devices 16 and the drain contacts D and the source contacts S of each of the plurality of FET devices 16, the body contacts B are also biased at the voltage −Vbias.
One of the problems with this approach is that it requires the negative voltage source 24 to maintain the gate contacts G at the negative bias voltage −Vbias relative to ground during the open state. The negative voltage source 24 may be implemented using negative charge pumps that add additional complexity to the control circuit 20 and may generate spurs. Furthermore, the additional DC voltage source 22 is required to provide a positive bias +Vbias to the gate contacts G, and to operate the FET device stack 14 in a closed state, which also adds complexity to the control circuit 20. If the negative voltage source 24 is implemented by the negative charge pumps, the finite output impedance of the negative charge pumps also causes problems during transitions from different states as connections to the gates and body are charged and discharged.
Another problem with the related art design is that it requires a bias swing of |2Vbias| to turn the FET device stack 14 from the open state to the closed state, and vice versa. During steady state operation, the bias voltage −Vbias has been selected so that voltage from the time-variant RF signal 18 does not cause the voltage at the gate contacts G to exceed the breakdown voltage, given the maximum and minimum voltage peaks of the time-variant RF signal 18. However, transition states are required so that the voltage between the gate contact G and the other drain and source contacts D, S of the FET devices 16 do not exceed the voltage handling capabilities of the FET devices 16 from the open and closed states. Of course, this adds additional complexity to the control circuit 20, as switches 26A-26E and/or logic level shifters are required to provide the appropriate gate and body voltages during each of these states. These switches 26A-26E of the bias control device 28 must be appropriately timed to avoid stressing the FET devices 16 during these transitions.
In addition, another disadvantage of the related art design is that the body contacts B must also be negatively biased if the plurality of FET devices 16 comprises the type of FET devices 16 that require body biasing. For example, in certain types of FET devices 16, internal reverse bias diodes that prevent the FET device stack 14 from operating appropriately are activated between the body contact B and the drain and source contracts D, S during the open state. If the internal reverse bias diodes are activated and a bias voltage −Vbias is not provided at the body contacts B during the open state, then the voltage drop from the drain contact D to the source contacts S of each of the plurality of FET devices 16 would be limited to the voltage of a reverse bias diode, around 0.6 volts. Thus, the related art design requires negatively biasing the body contacts B to −Vbias so that the reverse biased diodes are not reverse biased (or at least are not significantly reverse biased) during the open state. Also, the body contacts B must be transitioned back to ground when the FET device stack 14 operates in the closed state. This requires the control circuit 20 to have switches 26C, 26D and for the bias control device 28 to time these switches 26C, 26D appropriately. Other related art embodiments use floating body designs and may not include body contacts B or use self-biasing. However, related art floating body designs suffer from poor linearity.
Lossiness in the switchable capacitive element 10 also degrades the performance of the switchable capacitive element 10. One performance metric that is indicative of the lossiness of the switchable capacitive element 10 is a quality factor (Q factor) of the switchable capacitive element 10. The Q factor is a ratio of imaginary impedance to real impedance. With regard to the switchable capacitive element 10, the Q factor is an imaginary impedance of the switchable capacitive element 10 and a real impedance of the switchable capacitive element 10 when the FET device stack 14 is in the closed state. Since the imaginary impedance of the switchable capacitive element 10 is a function of frequency and the capacitance of the capacitor CRLW, the Q factor of the switchable capacitive element 10 is also a function of frequency. Unfortunately, the switchable capacitive element 10 can be excessively lossy, which results in lower-than-desired Q factors at RF frequencies.
Accordingly, there is a need to develop a switchable capacitive element with higher Q factors and/or with control circuits that do not require excessive bias swings and negative biasing voltages.